Research

As communications technology migrates towards wideband software-defined radios (SDR) and cognitive radios (CR), receivers are expected to dynamically acquire or monitor one or more signals of interest whose frequency locations, bandwidths, and interference scenarios may not be known apriori. Off-chip filters (e.g., SAW filters), which are employed in traditional receivers, provide the requisite sharp filtering but are too bulky, costly, and inflexible to satisfy the needs of SDR and CR. Integrated filters that meet the associated sharpness, linearity, and programmability requirements using existing filtering techniques are either impossible or prohibitive in terms of power, area, and/or cost.

Our group has been pioneering the use of periodically time-varying (PTV) components in receiver front end circuits as a digital-friendly means of achieving sharp filtering, excellent linearity, and low power consumption. This reverses decades-old dogma of using LTI systems along with at most a few mixers to achieve desired frequency down-conversions e.g., mixer-first and N-path approaches. For example, by dynamically changing the resistor value in a 1st order RC circuit in a pre-determined manner, and subsequently sampling the capacitor voltage, effectively an 8th order Butterworth filter can be realized! The LPTV circuit effectively appears as a sharp linear time-invariant (LTI) filter from the continuous-time input to the final sampled output of concern.

In the past, we have theoretically established the basis of this fundamentally new PTV technique [Rachid13] and demonstrated multiple prototype CMOS ICs based on this technique. Among them, we demonstrated multiple SDR receiver front-ends with sharp, programmable filtering [Hameed17, Hameed18], with the best reported linearity and blocker-tolerance at the time of publication. We also demonstrated a purely passive spectrum scanner with the best reported linearity and lowest reported power consumption [Sinha17]. Furthermore, we have developed a mathematical tool to analyze the performance of PTV circuits based on vector-extensions of traditional circuit laws such as KVL and KCL [Hameed16]. Note that analysis of PTV circuits involves incredibly tedious mathematics and has been one of main reasons behind the lack of their widespread adoption.

Most recently, we have developed a new slice-based circuit architecture that achieves PTV operation by combining a time-varying number of nominally linear time-invariant (LTI) slices. This allows much of the design to proceed using simple LTI intuition thereby addressing a basic difficulty in using PTV circuits. Furthermore, the slice-based architecture presents a mostly LTI input impedance allowing easy concatenation with other LTI circuits. We demonstrated carrier aggregation using the slice-based architecture with the lowest reported LO leakage and best reported linearity even at just 0.9V supply. Note that high LO leakage has been a significant problem with all varieties of mixer-first and N-path receiver prior art.

Currently, we are working on developing a technique to cancel any residual interferers that are not sufficiently suppressed by our PTV system. We will employ digitally controlled LMS techniques to maximize achievable residue cancellation [Bu22].

Traditional frequency/phase synthesis employs a power- and area-hungry oscillator in a low bandwidth negative feedback loop. While very successful so far, this approach is problematic in many applications that require either wide bandwidth e.g., radar and newer high-efficiency switching power amplifier architectures, or many clock signals e.g., MIMO and other beam-forming applications, or both. Open-loop frequency/phase synthesis, commonly clubbed under categories such as Direct Digital Frquency Synthesis (DDFS), fractional frequency division, digital-to-phase conversion (DPC) etc. can address these problems. However, these approaches are beset by circuit mismatch isses and exhibit unfavorable trade-offs between phase quantization noise, spur performance, modulation bandwidth and power consumption.

To break this trade-off, we have developed multiple techniques such our a predictive phase quantization noise cancellation [Su11] and automatic digital calibration to enable 10b ENOB performance [Nidhi17]. In all these cases, our prototype ICs achieved lower power consumption and phase noise than prior art in significantly more advanced technologies.

Recently, we have demonstrated an open loop DPC technique that generates multiple harmonically un-related, fractionally divided clock frequencies from a single high frequency low noise clock signal that achieved integrated jitter < 90fs and spurious tones < -103dBc on a 2.4 GHz [Hung19]. The spurious tones level is 33dB better than the best in prior art! The technique epitomizes our approach of using signal processing techniques to overcome circuit challenges. It leverages our work on the theory of dithered quantizers to generate a spur-free (but noisy) clock and uses it to digitally remove spurious tones in low-noise desired clock beset by spurious tones.

Currently, we are working on further advancing such digital spur cancellation techniques.

Clocks play a central role in IoT devices. Apart from their typical use in communications, localization, timing mixed-signal and digital logic units etc., they also serve as an always-ON time-keeper and provide timing for aggressive duty cycling of power-hungry blocks. The last two use cases have a great impact on overall system energy consumption of several IoT devices, and require clocks that are simultaneously stable and consume low energy. We have developed two important techniques that improve the state-of-the-art in IoT clocking: a technique to quickly startup a crystal oscillator (XO), and another technique to achieve sub-nW 32kHz XO operation.

Quickly starting up an XO allows aggressive duty cycling of parts of a system including the XO. This is extremely important to reducing overall energy consumption and prolong battery life in IoT and sensor nodes. Quick XO startup is a challenge that has resisted decades of research. Our simple solution involves pre-energizing the high-Q crystal for a short but precise duration. We have demonstrated, in a CMOS prototype, XO startup in just 100 cycles, which is about 20x faster than competition, and is far more tolerant of PVT variations [Esmaeelzadeh18].

We have also demonstrated the world’s first sub-nW 32kHz XO for real time clock applications, based on a new PTV sustaining amplifier that uses a DC-only sustaining amplifier [Esmaeelzadeh19]. Since this oscillator always stays ON to facilitate duty cycling of active circuitry in IoT devices, this promises to have a significant impact on IoT device battery life.

Currently, we are interested in addressing the stability issues of crytal-free clocking systems.

We are very interested in identifying algorithmic techniques that can condition the statistics of the error of coarse signal quantization. Since a large class of circuits e.g., ADCs, DACs, frequency/phase synthesizers, switching power amplifiers etc. process quantization error (along with the signal) in one form or the other, conditioning its statistics enables robust IC designs that are insensitive to circuit errors and nonlinearity. We identified sufficient and necessary conditions that guaranteed the elimination of limit cycles and spurious tones in digital delta sigma modulators [Pamarti07a, Pamarti07b]. We have also extended the theory to split- and time-interleaved delta sigma ADCs [Pamarti08a, Pamarti08b]. These conditions guide designers in the choice of digital delta-sigma modulators for applications such as fractional-N PLLs and oversampled D/A converters.

Furthermore, we have identified theoretical conditions that will ensure that quantization error in the presence of filtered digital dither is independent of the signal or at least uncorrelated [Ghosh13]. We applied this powerful technique to scramble the effect of tuning curve non-linearity in a VCO-based ADC and thereby improve its SFDR, resulting in one of the lowest figures of merit for this class of ADCs at the time of publication [Ghosh15]. More recently, we have applied the same technique to enable a spurious tone cancellation technique; it achieved the lowest reported spurious tones in a fractional frequency synthesizer to date [Hung19].

In the past, we have worked on several topics such as efficient switching power amplifiers, mm-wave clocking and power amplifiers, high speed I/O, and VCO-based data converters.

(A) Efficient switching power amplifiers: Poor efficiency of power amplifiers (PAs), particularly when operating well below peak power (back-off) conditions, has been a problem that has survived close to six decades of circuit research. Since most PAs, especially those amplifying complex modulation signals such as OFDM, operate rarely at peak power, this is one of the most important obstacles in improving the battery-lives of portable devices. Conventional linear power ampliers, such as Class A/B/AB PAs, achieve high linearity, but at the expense of high efficiency degradation on backoff. Switching PAs, such as Class D/E can achieve high peak efficiency (ideally 100%), but cannot track changes in envelope. Envelope tracking and other techniques can help but require efficient supply modulators that are challenging when bandwidths are high. To address this fundamental problem, we developed dynamic circuit reconfiguration techniques that modify the components of a switching PA, at high speed, intelligently, according to prior knowledge of desired instantaneous output power, such that it always operates along maximum effiency contours in its parameter space. We had established the theoretical basis of the technique and demonstrated discrete component and integrated prototypes in class-E and outphasing PA architectures [Singhal11, Singhal12, Shim15].

(B) High speed I/O: Differential-mode (DM) signaling has enabled multiple Gb/s data rates but at the expense of poor pin utilization (0.5 links/pin). Signaling over the common-mode (CM), in addition to DM to improve pin utilization, is also possible, but achievable data rates are low due to inevitable interference between the DM and CM signals caused from on-die and PCB trace mismatches, package parasitic, signal time of flight differences and electromagnetic coupling. We developed a technique based on the Code Division Multiple Access (CDMA) principle to suppress the signal crosstalk in multi-GHz multi-conductor signaling systems that employ simultaneous CM and DM signaling and demonstrated 3 links over 4 wires with an aggregate of 16 Gb/s in 90nm CMOS.

(C) VCO-Based Analog-to-Digital Converters (ADCs): VCO-based ADCs are simple to implement and scale well with CMOS process technology but are challenged by the non-linearity of the VCO tuning curve. This challenge is typically addressed by either making the VCO tuning curve more linear, or using analog crcuitry to reduce the dynamic range of the VCO-based ADC input, or by digital post-processing to correct for the non-linearity. The two former, analog, approaches inevitably increase the power consumption and do not scale well with technology. The latter, digital, technology scales well with technology, but the power consumption overhead can be significant when handling wide bandwidths even in finely scaled nodes. In radical contrast, we used special filtered digital dither to render the VCO-based ADC input mostly random and white so that the tuning curve nonlinearity doesn't cause undesired tones but random noise. Given the oversampling inherent in VCO-based ADCs, in-band SFDR and SNDR are substantially improved [Ghosh15]. The technique derives from our work on understanding the properties of dithered quantization.

(D) Mm-wave circuitry: Working in collaboration with Broadcom, our group members developed circuits to reduce the noise of mm-wave oscillators [Shirinfar13b], improve the efficiency of mm-wave amplifiers [Shirinfar15], and to linearize them locally for use in an array [Shirinfar13a].