UCLA CMOS Lab - Research

Over the history of integrated circuits, growth in performance and functionality has largely been achieved by scaling down the size of the Metal-Oxide-Semiconductor Field Effect Transistors (MOSFET). A gargantuan increase in speed and performance has been achieved due to this trend of scaling. In recent years, however, many daunting challenges arise as we scale into sub-50nm regime. New materials and design methodologies are being investigated to extract better performance. The main issues that arise as we keep pushing MOSFET scaling can be broadly classified as:

• Source-to-Drain Electrostatic Coupling
• Channel Transportation limitations due to mobility and velocity effects
• Parasitic Resistances and Capacitances
• Quantum Effects

The obvious approach would be to reduce or eliminate these effects by using various types of device architectures, such as double gate structures, strained channels, etc. and make the device more long channel like. A more creative approach would be to exploit new transport mechanisms and device physics which are made available due to the small dimensions as well as new materials. Also, due to the enormous infrastructure already in place for CMOS systems, it would also be very advantageous if the resulting devices can be easily integrated with the present technologies.

Our broad array of research topics includes novel semiconductor field effect device structures using innovative materials and concepts. Specifically, we are currently working on:

Novel Silicon Based Devices

• Asymmetric channel and gate devices
• Source Tunneling Devices (Schottky and Band-to-Band)
• Novel Vertical Devices (Double and Wrap-All-Around Gate)
• Novel Planar Double-Gate Devices

Innovative materials for future MOSFET generations

• SiGe and Ge channel devices
• Graphene based devices
• New gate stack structures (high-k and FUSI)

Device optimization for analog and switching applications

• High Speed CMOS Switches
• Device Optimization for Mixed-Mode Applications